With the development of network and Internet Protocol (IP) technologies, an IP network has changed from a network that provides only a data service to a network that provides several services, such as data, voice, video, and image. Due to features of different services, a device needs to use a quality of service (QoS) technology to provide QoS of different classes for data streams of different service types. Factors for evaluating QoS include a transmission bandwidth, a transmission delay, a packet loss rate, a jitter, and the like. Generally, QoS can be improved from several aspects, for example, ensuring a transmission bandwidth, reducing a transmission delay, reducing a packet loss rate of data, and reducing a jitter. Generally, a device implements, by means of a TM function, performance objectives, such as a transmission bandwidth, a transmission delay, a packet loss rate, and a jitter of a data stream. The TM function may be implemented in a protocol processing chip or a switching fabric chip, or may be implemented using an independent TM chip.
An independent TM chip can meet increasingly more service demands, increasingly large switching capacities and bandwidth demands, and increasingly high QoS requirements. Currently, a TM chip in a device is generally located on a data path between a central processing unit (CPU) and a switching fabric chip, as shown in FIG. 1. An interface of the TM chip needs to be consistent with a high-speed data interface of the data path, which causes that the interface of the TM chip is inflexible and complicated to implement. In addition, the TM chip needs to use a high-specification field programmable gate array (FPGA), such as STRATIX series of ALTERA Corporation and VIRTEX series of XILINX Incorporation in order to meet a requirement of a TM function, logical processing, and performance. Furthermore, in addition to a processor or a switching fabric chip, a dedicated external storage unit, such as a double data rate synchronous dynamic random access memory (DDR SDRAM) or a quad data rate synchronous dynamic random access memory (QDR SDRAM), needs to be equipped to store a data packet and related information. The TM chip also needs to be equipped with a dedicated external storage unit, such as a DDR SDRAM or a QDR SDRAM, to store a data packet and related information, thereby causing a relatively high cost.